1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method that minimizes the size of the semiconductor package almost to the size of a semiconductor chip and improves an electrical path between a chip pad and the outside to enhance electrical characteristics.
2. Background of the Related Art
In the construction of a related art semiconductor package, a semiconductor chip is fixedly bonded on a paddle of a lead frame. Then, the pads of the semiconductor chip and internal leads are electrically connected with conductive wires. Next, the entire structure is sealed with a molding resin. Finally, the external leads are formed to be of a predetermined shape depending on the intended use.
FIG. 1 is a cross-sectional view showing an SOJ (small outline J-lead) semiconductor package in which external leads 7 are formed in the shape of a letter "J". As shown in FIG. 1, internal leads 3 of a lead frame are bonded on a semiconductor chip using the strength of an adhesive tape 2. Further, chip pads 6 formed at the center of the top surface of a semiconductor chip 1 are connected with the internal leads 3 through conductive wires 4 using ultrasonic thermal compression bonding. Then, the semiconductor chip 1 and the internal leads 3, except for the external leads 7, are surrounded within a molding resin 5. Finally, then the external leads 7 are formed depending on the purpose of the user. The external leads shown in FIG. 1 are formed to be "J" leads.
In the related art semiconductor package, an electrical signal from the chip pads 6 formed on the semiconductor chip is transmitted outside the semiconductor package using the lead frame. However, the package size is relatively large in comparison with the semiconductor chip size. As the electrical path from the chip pads to the external leads become longer, the electrical characteristics decline and a semiconductor package with many pins is difficult to achieve.
To overcome the disadvantages of related art semiconductor packages using the lead frame, various kinds of semiconductor packages such as a chip-size semiconductor package have been developed.
FIG. 2 shows a plastic molded extended bump (PMEB) type chip-size semiconductor package. In FIG. 2, a metal wiring pattern 13 is formed to connect a plurality of chip pads 12 formed on the semiconductor chip 11 with internal bump bonding pads 17. On the internal bump bonding pads 17 are bonded conductive internal bumps 16. On the top surfaces of the conductive internal bumps are bonded tapes (not illustrated). Then, the semiconductor chip 11 is surrounded within a molding resin 14. By removing the tapes (not illustrated), the top surfaces of the internal bumps 16 are exposed. After applying a solder paste to the internal bumps 16, conductive external solder balls 15 are put thereon and bonded with the internal bumps 16 through an infrared reflow process. Such a PMEB-type chip size semiconductor package was described at the "SEMICON JAPAN '94 SYMPOSIUM" held by the MITSUBISHI corporation in Japan on Dec. 2, 1994.
FIG. 3 is a cross-sectional view of a bump electrode in FIG. 2. The chip pads 12 are formed on a top surface of the semiconductor chip 11. A passivation film 18 that protects the chip 11 is formed on the semiconductor chip 11 except on the top surface of the chip pads 12. The metal wiring pattern 13 is formed on the chip passivation film 18 having one end connected to the chip pads 12 and the other end connected to the bump bonding pads 17.
The metal wiring pattern (ball connecting pattern) for transmitting electrical signals from the chip pads 12 is formed through a separate pre-assembly formation process. That is, the metal wiring pattern 13 is formed to electrically connect the chip pads 12 of the semiconductor chip 11 of the semiconductor chip 11 to the internal bump connecting pads 17. A polyimide film 19 is formed on the above construction except the internal bump bonding pads 17. Next, the internal bumps 16 are bonded on the exposed internal bump bonding pads 17 by means of a solder adhesive 20 composed of Pb or Sn. Then, the molding resin 14 seals the semiconductor chip 11 by surrounding the entire surface of the above construction except for the top surface of the internal bumps 16. Finally, the external balls 15, which serve as external leads, are bonded on the internal bumps 16 to complete the chip-size semiconductor package fabrication.
The overall size of the PMEB-type chip-size semiconductor package relative to the related art SOJ semiconductor package is smaller. Further, the PMEB-type semiconductor package has a relatively shorter electrical path, which improves the chip's electrical characteristics. However, a separate formation process, which is a pre-assembly process, is necessary for the metal wiring pattern. Further, the electrical path from the chip pads of the semiconductor package to the external solder balls remains relatively long.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.